Asia-Pacific Workshop on FPGA Applications

ISSN 2310-4422(ONLINE)   ISSN 2305-9877(PRINT)   ISSN 2310-1059(CD)

2013
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  • CN003  Design and Implementation of Load-Balanced Multipath Self-routing Switching System
    Qian Zhan, Zhi-Pu Zhu, Li Ma, and Hui Li, Member, IE
    School of Electronic and Computer Engineering, Peking University

    Abstract— In order to ensure high quality of service (QoS) for Next Generation Network (NGN), we construct a new Load-Balanced Multipath Self-routing Switching Structure which consists of the same two multipath self-routing fabrics. The result of simulation is inspiring for achieving 100% throughput and no delay or jitter. For this reason, we start on the implementation on an Altera StratixIV FPGA. And the whole FPGA system is designed into two collaborative components: the UDP system and the register system. With two algorithms around input and output two stages, incoming traffic is transformed into uniformity and then to their final destinations. During the later period debugging, software simulation platform and automated test platform are built, which contribute to our work very much. At last, we carry out several experiments to test and verify our system. The report of the test result accords with what we expected.
    Keywords— Load-Balanced; Multipath Self-routing Switching Fabric; FPGA; UDP; Register

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  • CN011  Design of Entropy Decoding Module in Dual-Mode Video Decoding Chip for H. 264 and AVS Based on SOPC
    Hong-Min Yang, Zhen-Lei Zhang, and Hai-Yan Kong
    School of Information Science and Engineering, Shandong University

    Abstract— This document introduces the hardware design of the entropy decoding module in dual-mode video decoding chip for H. 264 and AVS standard. The entropy decoding module designed in this document can realize the decoding of CA-2D-VLC for AVS standard and CAVLC and CABAC for H.264 standard. The Verilog HDL is used to accomplish RTL design and the FPGA implementation is achieved on an Altera Cyclone II EP2C35F672C6. The result indicates that the design efficiently reduces the circuit area and improves the speed of decoding.
    Keywords— H.264; AVS; entropy decoding; FPGA; Verilog HDL

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  • CN014  Design and Implementation of DES IP Based on LEON3 SOPC
    Jing-Jiao Li, Chao-Qun Rong, Dan-Yang Peng, and Dong An
    Institute of Electronic Science and Technology, Northeastern University

    Abstract— This paper proposes a novel method to design and implement DES algorithm IP based on LEON3 SOPC platform. Since this DES IP core is a standard AMBA APB slave device, it can be easily embedded to SoC designs where AMBA bus is used as the interconnect interface, making it much more effective to implement DES algorithm in SoC designs. So comparing with common hardware implementation of DES algorithm, this DES IP core has a very large application prospects in SoC designs. Also the method this paper presents to design an AMBA APB slave device in LEON3 architecture can be referred to. The DES IP is simulated by Modelsim and tested within the LEON3 SOPC platform. Results indicate that this DES IP core has a fine performance and the method this paper demonstrates to design and implement an APB slave device is reliable and referable.
    Keywords— DES; IP; LEON3; AMBA; SoC; SOPC

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  • CN034  Intelligent Parking System Based on Nios II
    Ping-Ping Meng, Kai Pei, and Pei-Rui Li
    Communication Engineering, Chongqing University

    Abstract— Intelligent parking system attracted increasing attention of the automobile manufactures in recent years. A reliable parking assistant system could reduce the rate of accident effectively and simplify the operation of the driver. This design takes Nios II as control core, uses camera to collect parking information, installs ultrasonic sensors to achieve ranging capabilities, adopts Ethernet port and wireless router to realize communication with Android smart phone and designs driver circuit to control car. The experiments show that this design can achieve real-time operation of the model car through smart phone to finish parking process. Meanwhile the car can complete parking automatically with the assistance of image and range information.
    Keywords— Intelligent Parking; Nios II; FPGA; Android; Realtime Image Processing

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  • CN039  An Eye Controlled System Based on Nios II
    Wen-Jie Ye, Ke Huang, and Qiu-Xiang Chen
    College of Communication Engineering, CHONGQING University

    Abstract— In the background of current hot sight-tracking technology , this topic aims at designing an eye controlled system based on Nios II and solving the HMI problems of the disabled so that it can provide a way for them to communicate with the outside world, improve their ability of living and help them regain confidence. We have also designed some Interactive functions such as an eye controlled calculator, an eye controlled Whac-A-Mole game and an eye controlled voice-help. It can provide convenience and help them communicate with others, seek help, have fun and study.
    Keywords— SOPC; VGA display; Image Processing; Relative Offset Calculation; View positioning; Edge detection

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  • CN040  The Intelligent Detecting Robot
    Yan Zhang, Qing-Shan Wang, and Jie Wen
    College of Automation, Harbin Engineering University

    Abstract— With the current advanced SOPC technology carrier, intelligent detection robot system is designed. Using the DEII board of ALTERA company as the robot‘s control core, we realize the robot’s navigation and positioning, environmental information detection and the function of information transmission. Detection robot system transmits the position and spot environmental information to the PC monitor, this can help operators to judge the scene of the accident situation for effective rescue work.
    Keywords— Detecting robot; FPGA; DEII; GPS; EC

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  • CN050  Towards Wearable Virtual Reality System Using Micro IMU Controller and FPGA Platform
    Wen-Xian Wu, Yan Shao, and Quan-Biao Chen
    School of Software and Microelectronics at Wuxi, Peking University

    Abstract— Virtual Reality (VR) is a computer-simulated environment that can simulate physical presence in places in the real world or imaginary world. We use FPGA to implement this design to take advantage of its hardware/software co-design and its high computation speed. We use IMU as the main input. It captures and sends motion data to FPGA. FPGA plays an important role in this system. It drives hardware, processes data, and stores and manages pre-stored image or sound material. After processing, system outputs image and voice, and imports into media glass and speaker, which are used as output devices, respectively. The final result shows that our system designed with FPGA can run fast and smoothly, easy to maintain and update, and it shows great potential.
    Keywords— FPGA; co-design; virtual reality; sensor; media glasses

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  • CN051  Galaxian Game on Altera DE2-115 FPGA Architecture
    Si-Ming Xia, Xiao-Le Xu, Liang Qin, and Chang-Hua Liu
    School of Mathematics and Computer Science, Wuhan Polytechnic University

    Abstract— With the development of computer and network technology, the pace of people’s life is much faster. At the same time, the need for entertainment is also growing. The game based on handheld devices is becoming more and more popular. It has been booming along due to its educational, fun, casual, easy to carry, easy to operate, highly interactive and many other features to meet the people's entertainment needs. This paper introduces the embedded systems based on general-purpose software development model and development process, including the design of hardware platform and software. The design of the hardware platform is based on the Altera's DE2-115 Series development board, the software platform is Nios II EDS 10.1 and the programming language is C and VHDL. Based on the SOPC tool, we designed the reconfigurable IP cores of the VGA display, LTM touch screen. With Galaxian game as an example, we design a embedded game based on GUI. The results show that the game system is human-computer interaction friendly and it has quick response and action. This configurable IP core has high flexibility, variability, plasticity and it can achieve more functional expansion and development with the same resource.
    Keywords— Configurable IP core; DE2-115; FPGA; SOPC; hardware/software co-design

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  • CN053  Implementation of Music Broadcast System Using Altera DE2 Boards and Qt
    Cheng-Long Zhao, Hui-Bin Shi, Qiao-Zhi Sun, and De-Chun Kong
    Department of Computer Science and Technology, Nanjing University of Aeronautics and Astronautics

    Abstract— This paper will introduce a music broadcast system based on schedule using Altera DE2 boards and Qt technology. The system has Client/Server architecture. Qt technology is used to set up a server in Ubuntu operation system. It will manage all online DE2 boards and send commands to them to play music stored on SD card inserted into the board.
    Keywords— FPGA; Scheduled Music Broadcast; Qt; Nios II

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  • CN058  Intelligent License Plate Positioning Identification System Based on FPGA
    Hu-Cheng Xie, Mi Zhou, and Pei Zhang
    College of Educational Information and Technology, Hubei Normal University

    Abstract— With the rapid development of China's national economy, intelligent transportation systems has become the main direction of the development of traffic management, and license plate recognition system technology as the core of intelligent transportation system plays a pivotal role. This paper describes a theory based on Altera's CYCLONE II EP2C35 devices on the platform location and license plate recognition system. The system mainly works like this: First, camera module reads a license plate image, then through the image plate rough positioning, image graying, median filter, sobel operator edge detection, image binarization, plate processing such as automatic positioning precision positioning plate, and also through the establishment of NIOS II soft-core processor for the license plate character segmentation, and then match a single character segmentation, license plate recognition. In this system, some of the basic positioning using Verilog hardware description language, implemented in hardware for parallel processing large amounts of data, processing speed, high accuracy. For image positioning plate, color image based positioning methods; the algorithm is simple, less memory, which makes it possible to achieve fast and accurate positioning plate. License plate segmentation algorithm uses the traditional template matching algorithm. By establishing SOPC system allows users more easily to interact through the software license plate recognition, thereby provides greater flexibility.
    Keywords— license plate positioning; FPGA; the image processing; Character segmentation

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  • CN059  Modified Visual Target Tracking Algorithm and Its FPGA Implementation
    Zhi-Ying Du, Shu-Hui Wang, and Dong-Bin Pei
    School of Communication and Information Engineering, Shanghai University

    Abstract— Visual target tracking is the key problem in intelligent video processing. CamShift and Particle Filtering are classic and effective in visual target tracking algorithms, but they both need to analyse a large amount of probability statistic, leading to high algorithm complexity and low calculation efficiency. FPGA provides a competitive alternative for hardware acceleration to these applications. In this paper, we modify CamShift and Particle Filtering algorithms and propose a FPGA-based hardware accelerating architecture. Experiments show the embedded architectures have good performance and the Particle Filtering algorithm shows better robustness and real-time performance.
    Keywords— target tracking; CamShift; Particle Filtering; FPGA; embedded system

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  • CN060  A Lane Departure Warning System Based on Monocular Vision
    Bai-Rui Zhang, Wei-Xiong Lu, and Song-De Zeng
    Electronic Circuit and System, South China Normal University

    Abstract— This paper introduces a monocular-vision-based lane departure warning system. Based on a fast lane departure warning robust algorithm and the NIOS II of Cyclone IIFPGA as the core processor, this system can achieve the lane line detection effectively. The software and the hardware of the system are designed with the aid of the Avalon bus for customizing the IP core. Test results illustrate that both the accuracy and real-time performance of this system satisfy the demand of all-weather lane departure warning, and thus enable safe driving.
    Keywords— lane departure; FPGA; lane line detection; monocular-vision

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  • CN063  Intelligently-Controlled Quadrocopter with Autonomous Navigation using Android
    Hong-Wei Shi, Xing-Liang Wen, and Ming-Li Zhao
    Chongqing University

    Abstract— A quadrocopter is a new kind of unmanned aircraft that has the advantages of novel structure and excellent performance, relating to high, exact and sophisticated technology in many fields. It is of value to practical applications. At first, our team studied a quadrocopter’s structure characteristics, attitude algorithm and flight control principle. Then a flight control system was designed which uses LB0 (LB0 employs EP3C10E144C8 of Altera Cyclone Ⅲ as core device) and MPU-6050 as core device and inertial measurement device respectively. The system analyzes the control signal which android mobile phone sends by WIFI, fuses current sensor measurement data, estimates the aircraft’s motion attitude and then calculates the motors adjustments. According to the motors adjustments, the system controls the motors to regulate the quadrocopter’s flight attitude. It results in a good effect that Euler angles method and Kalman filtering algorithms are adopted to describe and calculate the attitude respectively. At the same time, the data from GPS module is transmitted back to android mobile phone by WIFI and then it helps the system realize autonomous navigation.
    Keywords— Quadrocopter; Android, Intelligent Control; Autonomous Navigation; FPGA

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