Asia-Pacific Workshop on FPGA Applications

ISSN 2310-4422(ONLINE)   ISSN 2305-9877(PRINT)   ISSN 2310-1059(CD)

2012
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  • Contributing Author

     Applying Research Outcomes into Innovation and Technology for Better Health Care and Life Quality

    Yin Chang
    Department of Biomedical Engineering, National Yang-Ming University

    Abstract—The history of medicine can be traced back to the ancient human societies that related to the beliefs which provide explanations for birth, death, and disease. However, the concepts of diagnosis, prognosis, and medical examination were not formed until introduced by ancient Egyptians in Africa (1600 BC), Babylonians in Mideast (2200 BC) and Chinese in Asia (1600 BC). Preventive medicine was also developed in China at that time. During the Renaissance, knowledge of understanding anatomy and the invention of the microscope led to the ‘germ theory of disease’, the foundation of modern medicine. Now we are in the 21 century, standing on the summit of modern medicine era, which our ancestry had never dreamed of. Our life has already been extended from an average of 25 years in the Stone Age to around 70 years in the ‘Modern Age’ due to the help of modern medicine. However, we still face to many incurable diseases, such as cancer, AIDS, cardiovascular disease, psychiatric disease…etc., even our technologies in pharmacology, chemistry, physics, biology, medicine and engineering have tremendously improved than before. How to apply our research outcomes into innovation and technology for better health care and quality of life should be our mission and obligation.

    Keywords— History, medicine, disease, technology

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  • 001  Implementing Full HD Video Splitting on Terasic DE3 FPGA Platform
    Rosaline Lin
    Terasic Technologies

    Abstract— This document introduces the design of HDMI Full HD 1080p splitting processor techniques in detail. It also describes how to design the proper DDR2 Multi-Port Controller to prevent the side effects of image processing like flickering and tearing. In addition to this, it shows how the DDR2 Multi-Port Controller gets the best performance, where the DDR2 can operate easily at 200 Hz with a 148.5 MHz Full HD input source, and hence there is no limit number of screen splitting.
    Keywords— video split, DDR2 controller, Multi-Port memory controller, ping-pong buffer, TV wall

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  • 002  Design of Large-scale Wire-speed Multicast Switching Fabric Based on Distributive Lattice
    CUI Kai, LI Ke-dan, CHEN Fu-xing, ZHU Zhi-pu, ZHU Yue-sheng
    Peking University, Shenzhen Senior High School, Peking University, Peking University, Peking University

    Abstract— Ensuring high quality of service (QoS) of multicast video stream over a next generation network is a challenging issue, and how to implement the wire-speed multicast with hardware logical support in the network nodes of every hierarchy is a key solution to achieve high QoS multicast. Currently, the multicast packets are processed in this way, in which they are copied and then scheduled by ports, lastly, sent respectively. But this approach cannot ensure the high QoS in real-time applications. Moreover, the traditional hardware solutions can`t achieve large-scale scalability well owning to their own bottlenecks. In this project, using distributive lattice theory we have constructed a wire-speed multicast switching fabric based on a multi-path self-routing fabric structure which we developed previously, and implemented it on an Altera StratixIV FPGA chip. Also, we have investigated how the structure is used in large scale multicast switching fabric and designed the signaling system and control mechanism to support the process of self-routing and wire-speed fan-out copy of multicast packets.
    Keywords— multicast switching fabric, distributive lattice, Multi-path Self-routing Fabric Structure, FPGA

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  • 003  FPGA Implementation of an Efficient Two-dimensional Wavelet Decomposing Algorithm
    Chuanyu Zhang, Chunling Yang, Zhenpeng Zuo
    School of Electrical Engineering, Harbin Institute of Technology Harbin, China

    Abstract— As the preferred method for the multi-resolution analysis of the image, discrete wavelet transform has gained more and more attentions. In this paper, a new VLSI architecture is designed to finish two-dimensional all at once. Through further derivation of the transform formulas, line based method is improved and the circuit structure is simplified. The FPGA implementation has been achieved on an Altera Cyclone II EP2C35F672C6. Results show that this improvement results in a considerable performance gain while reducing the consumption of on chip memory space and shortening output latency significantly. Under pure calculation logic, processing speed reaches 157.78MHz.
    Keywords— wavelet transform, image processing, FPGA, VLSI, SOPC

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  • 004  FPGA Implementation of a Multi-Core System Architecture for Power Adaptive Computing
    HUANG Le-tian, Fang Da
    University of Electronic Science .and Technology of China

    Abstract— By analysing the system requirements of Power Adaptive Computing System, a Multi-core system is designed. The system has one master core for management and four slave cores for computing. A sharing bus structure and a special communication mechanism are designed. Based on the sharing bus and the communication mechanism, master CPU could schedule the tasks and control each slave CPU core. The architecture is simulated by modelsim and is verified based on FPGA. The result shows that the system the whole process of can successfully complete from tasks assigned to the result returned in this system.
    Keywords— Multi-Core Architecture, FPGA, Power Adaptive Computing, Bus structure

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  • 005  Introduction of the Research Based on FPGA at NICS
    Rong Luo
    Nano Integrated Circuits and Systems Lab, Department of Electronic Engineering, Tsinghua University

    Abstract— This document introduces the research work based on FPGA at Nano Integrated Circuits and Systems Lab, Department of Electronic Engineering, Tsinghua University.
    Keywords— WSN Digital Baseband SOC, Two- dimensional Bar Code, Dynamic Time Warping Distance, Real Time Image Processing, FPGA

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  • 006  SOPC-based VLF/LF Three-dimensional Lightning Positioning System
    Xiao Zhou, Sheng Chang, Qijun Huang, Qiming Ma and 1Gaochao Gong
    Wuhan University, Wuhan University, Wuhan University, Wuhan University and China Meteorological Administration, Wuhan University

    Abstract— Lightning monitor technology is developing on the orientation of high accuracy, multi-lightning detect, three-dimensional monitor and lightning positioning. An SOPC-based VLF/LF three-dimensional lightning positioning system is presented in this paper. On the Altera’s Cyclone II platform, a Nios II embedded CPU is constructed. Through the AVALON bus, hardware modules, such as the controller of the signal collection board, the AD’s controller, the processor of lightning signal, the synchrotimer, the smoothing filter, the Zigbee controller, the network interface and the memory management IP, communicate with the CPU. This hardware-software collaboration structure efficiently decreases the complexity of the design and improves the system’s flexibility. Based on the lightning detecting instrument, a three-dimension lightning positioning network is setup. Through the multi-station time difference of arrival (TDOA) algorithm, the network can detect a thunderstorm’s generation, progress and attenuation, which is important for both the research and the early forecasting of the thunder.
    Keywords— lightning, three-dimensional positioning, time difference of arrival, field programmable gate array, thunderstorm

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  • 007  3D Position Tracking of Instruments in Laparoscopic Surgery Training
    Shih-Fan Yang, Ming-Feng Shiu, Bo-Kai Shiu, and Yuan-Hsiang Lin
    National Taiwan University of Science and Technology

    Abstract— The VR laparoscope surgery training device is for junior hospital students to understand and train the laparoscope surgery. However, those developing training devices use special instruments for their training program, not real instruments. Therefore, this paper developed a surgery instruments’ 3D location system for a VR laparoscope surgery training device while using real instruments. Moreover, this paper introduces a new method for hardware design in FPGA. This new method is using MATLAB’s tools to develop the algorithm, generating the HDL and verifying the FPGA system. The system in this paper has less 1% error in the central operating area and could calculate two instrument positions every 200ms on the Altera’s DE2-115 development platform. Thus, it could be employed in the VR training program.
    Keywords— Laparoscope surgery, Laparoscope surgery training, VR Laparoscope surgery, FPGA, 3D locating, HDL coder, FPGA In the Loop, FIL, MATLAB, Simulink

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  • 008  Air Guitar on Altera DE2-70 FPGA Architecture
    Ger Yang, Tzu-Ping Sung, Wei-Tze Tsai, and Shao-Yi Chien
    Department of Electrical Engineering, National Taiwan University

    Abstract— Air guitar is a well-known competition all over the world. It gives us a passion for those who might not play the guitar so well can be indulging in the magic power of guitar as well. However, although one may act so seriously as if he/she has a guitar, the sound would never be produced. Therefore, by capturing the user’s movement, we proposed a real-time and equipment-free system to make air guitar not only acting but also an alternative and user-friendly way to play the guitar.
    Keywords— Air Guitar, FPGA, Real-Time, Gesture Detection

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  • 009  Autostereoscopy Image Display System
    Du Lei, Tang Wenlong, Ye Peng, and Liu Hailong
    Faculty of Physics and Electronic Engineering, Hubei University

    Abstract— The proposed work presents a naked eye 3D display technology programs, including the holographic video acquisition subsystem and 3D rectangular pyramid holographic imaging subsystem. The holographic imaging acquisition subsystem consists of two DE2-70 multimedia development boards which implement real-time multi-angle acquisition of data video and the compositing and output of holographic video; the 3D pyramid holographic imaging subsystem uses the see-though material as the display media. The output holographic video of HVAS is projected onto the respective sides of the quadrangular and then floated image with a 360° viewing range in the quadrangular pyramidal internal. Hence, this display program perfectly matches with the real environment and creates living and stunning visual effects.
    Keywords— 3D Pyramid hologram, DE2-70, VIDEO PROCESS, NTSC, MULTI-PORT-SDRAM

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