UK001  The BERIpad Tablet: Open-Source Construction, CPU, OS and Applications
A Theodore Markettos, Jonathan Woodruff, Robert N M Watson,Bjoern A Zeeb, Brooks Davis, Simon W Moore
University of Cambridge, University of Cambridge, University of Cambridge, University of Cambridge, SRI International, University of Cambridge

Abstract— We present a full desktop computer system on a portable FPGA tablet. We have designed BERI, a 64-bit MIPS R4000-style soft processor in Bluespec SystemVerilog. The processor is implemented in a system-on-chip on an Altera Stratix IV FPGA on a Terasic DE4 FPGA board that provides a full motherboard of peripherals. We run FreeBSD providing a multiuser UNIX-based OS with access to a full range of generalpurpose applications. We have a thorough test suite that verifies the processor in continuous integration. We have open-sourced the complete stack at beri-cpu.org including processor, systemon- chip, physical design and OS components. We relate some of our experiences of applying techniques from successful opensource software projects on the design of open-source hardware.
Keywords— Open-source, hardware, tablet, FPGA, Bluespec,BERI, MIPS, FreeBSD, Terasic, Altera

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TW005  Fast Contrast Enhancement Based on A Novel Dynamic Histogram Equalization Algorithm
Shao-En Chiang, Chi-Chia Sun, and Chun-Ying Lin
Department Of Electrical Engineering, National Formosa University

Abstract— In this paper, a novel contrast enhancement algorithm based on the Histogram Equalization algorithm is presented. The proposed approach enhances image/video contrast without losing the original histogram characteristics. The algorithm is expected to process the video resolution efficiently but does not to overshoot the equalization with annoying side effects by using the difference information from the input histogram. The experimental results show that the proposed Dynamic Histogram Equalization (DHE) algorithm not only keeps the original histogram features but also enhances the contrast with much less computational efforts for large resolution. Furthermore, the proposed DHE algorithm can be easily applied to the FPGA hardware.
Keywords— Contrast Enhancement; Histogram Equalization; Dynamic Histogram Equalization; FPGA

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TW006  Design of Power Quality Recognition Platform
Shao-Ping Lyu, Men-Shen Tsai, and Chih-Hung Lee
Graduate Institute of Automation Technology, Graduate Institute of Automation Technology, Graduate Institute of Mechanical and Electrical Engineering, National Taipei University of Technology

Abstract— In recent years, the Taiwanese government has been actively promoting industrial upgrading, as a result, most technology-oriented industries are benefiting a lot from this. However, poor power quality increases the power consumption and reduces the life expectancy of the equipment. Hence, power quality problems gradually arouse public attention. In this thesis, an SOPC-based power quality analyzer (PQA) is designed. The main objectives of the proposed system are detecting transient voltage variations as well as analyzing the power harmonic interference. The transient voltage variation detection calculates the RMS value within a moving window length of half cycle. The harmonic analysis is performed with the application of Fast Fourier Transform (FFT) according to the requirements of IEC Std. 61000-4-7. The experimental results show that the proposed PQA is capable of detecting and capturing the power quality events.
Keywords— Power Quality; Transient Voltage Variations; Harmonic Analysis; Moving window; Fast Fourier Transform

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TW011  Design and Implementation of Intelligent Desk Lamp
Yu-Ping Liao1, Pang-Tzu Liu2, Jing-Xiang Cao3, and Ko-Chi Wei
Department of Electronic Engineering, Chien Hsin University of Science and Technology

Abstract— In this paper, we proposed a FPGA based intelligent desk lamp system with a camera, two servo motors and LEDs. The proposed lamp can trace a moving book by automatic pan/tilt control. Thus, the user can read book with enough light for eye care. The architecture of the intelligent desk lamp system includes vision system and servo motors control system. The position data of the book can be obtained by the image processing module. According to the position data of the book, the pan and tilt angles of the desk lamp can be adjusted by two servo motors automatically. The adjustable ranges for pan/tilt are 60/30 degrees. The processing modules are implemented by hardware in FPGA. We use Verilog HDL to implement this system on Altera DE0-Nano kit with Cyclone® IV EP4CE22F17C6N FPGA.
Keywords— FPGA; Intelligent Desk Lamp; Image Processing; Servo Motor Control

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TW012  FairyTales – Fairly Detailed
Shao-Hua Sun, Yao-Hung Tsai, and Chi-Wen Cheng
Department of Electrical Engineering, National Taiwan University

Abstract— This document gives a detailed explanation about the design of our product and the implementation of it. The name of our product is FairyTales, which is a visual assistant with respect to some extending function such as taking photos and real-time handwriting. The functionalities of FairyTales are realized through DE2-115 board which is a powerful equipment designed for to create, implement, and test digital designs using programmable logic.
Keywords— FairyTales; auxiliary eyeglasses; augmented reality (AR); vision system; DE2-115; Innovate Asia; Altera

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TW013  NeverFull
Yu-Ting Chou, Guo-Ting Wang, and Nae-Chyun Chen
Department of Electrical Engineering, National Taiwan University

Abstract— In modern world, high-tech products are widely applied to all kinds of industries. However, in restaurants and bakeries it still requires a lot of human resource that costs a lot and is likely to make mistakes. NeverFull provides powerful functions to recognize different types of food. Shop owners can build the database easily by themselves to save a lot of time and effort.
Keywords—

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TW015  A Real-time Object Detecting and Tracking Design for Railroad Crossing Application
Shih-Lun Chen, Chi-Hao Liao, Hao-Cheng Yu, Tang-Yu Lee, and Ting-Lan Lin
Department of Electronic Engineer, Chung Yuan Christian University, Taiwan

Abstract— As the promotion of transportation construction, there are a lot of railroad crossings in Taiwan. However, the traffic accidents are always happening on the railroad crossings every year. In order to protect the drivers against the accidents on the railroad crossing, an object detecting and tracking design is proposed for an automatic warning system. Since it is necessary to identify a vehicle getting stuck on the railroad crossing or not in a very short time, the very large scaled integration (VLSI) technique was used to develop the image processor for this system. This design not only detects any vehicle getting stuck on the railroad crossing or not but also tracks all vehicles across the railroad crossing. This double checking is guaranteed to the driver’s life. This design was realized by hardware description language (HDL) verilog and realized by an Altera DE2-115a field programmable gate array (FPGA) development board. By using the VLSI technique, this design has the benefits of high performance, low cost, and low power consumption. The accuracy of vehicle detection can be greatly improved with the combination of object detecting and tracking techniques.
Keywords— Feature extraction, FPGA; object detection; object tracking; railroad crossing; VLSI

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TW017  Vision-Based Robot Motion Control System by Using a SOPC System
Yi-Shiun Lin, Yi-Ting Chen, and Ching-Long Shih
Department of Electrical Engineering, National Taiwan University of Science and Technology

Abstract— This thesis presents a SOPC-based servo motion control technique for the robot manipulator system. The system adopts MATLAB to perform image processing functions, such as the transformation of the color space, morphological operation, data classification of the object, the shape recognition and endpoint detection. For the servo motion control of the robotic system, it consists of two controller modules. The first one control module is consisted of quadrature encoder pulse circuits, limit switches detection, generation of pulse width modulation ,and point-to- point motion trajectory generator. Then, control signals are sent via FPGA to drive circuits for controlling each motor. The other module which includes a user interface and calculation of inverse kinematics, which is implemented via the NIOS II.
Finally, user can send commands via PC to perforem the shape recognition, data classification of the object’s color, and play tic-tac-toe games on the basis of image processing. The experimental results have demonstrated the effectiveness and validity of the proposed FPGA system applied on the servo motion control of the robot manipulator system.
Keywords— SOPC; Arm Robot Motion Control; Image Processing

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TW018  Applying Dynamic Hair Dyeing Simulation On FPGA to Improve User Experience and Life Quality
Han-Ching Ou and Po-Jung Chang
Department of Electrical Engineering, National Taiwan University

Abstract— The purpose of this paper is to design a system avoiding user from getting unexpected hair dyeing result on FPGA DE2-115 which can perform real-time dyeing simulation.
In the system, user can have 55 default hair types, which have already been set in the devices, commonly used in hair salons. If there is a new hair color type that is not in those 55 defaults, the hair salon can adjust the value of red, blue, and green until the exact color result is obtained and then added to the system. The color information in RGB values will be showed on the LCD screen and the hair salon can easily change them only by a few ticks on the multi-touch board.
The system design architecture is consisted of three major parts. First, the camera collects the information and transports the data into the FPGA board. Second, the FPGA board processes and then an algorithm is applied to identify the correct region to be dyed. Also, in order to keep the hair texture, another algorithm is applied to imply for color scaling in the detected region. Finally, the multi-touch board displays the processing results and ready to receive user commands from the FPGA board. The system provides a more efficient and precise way to simulate the dyeing results of user in real-time compared to the common method in dyeing hair by just using imagination based on category.
Keywords— Hair dyeing; FPGA; Real-time; Hair detection; Color scaling

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TW019  iCoach – Interactive Coaching System on Altera DE2-115 FPGA Architecture
Hsin-Yu Lai, Guan-Lin Chao, Meng-Ting Zhong, and Shao-Yi Chien
Department of Electrical Engineering, National Taiwan University

Abstract— In this paper, we present a new interactive, 2-player coaching system – iCoach, based on Altera DE2-115 FPGA board. The coach can be the 2nd player or any video stream provided by the user. With beautiful virtual background image and different background music choices, he/she can enjoy exercising with the coach and get real-time scores and comments on the performance of their overall motion, thus improving their motor skills. Also, iCoach provides interactive motion games for users to have fun dancing and painting with body parts. In comparison with existing motor learning devises such as Wii Fit, iCoach is more flexible since it enables users to set up their own coaches and virtual environments. Moreover, iCoach is more computationally efficient and uses less memory due to the carefully designed algorithms and the arrangement of FPGA memory.
Keywords— FPGA; Dance; Coach; Motion-sensing; Interactive game; Rehabilitation

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TW021  FPGA Platform for Realtime 3D Reconstruction of Digital Holograms
Chien-Ting Chen, Tzu-Hsin Chuang, Jheng-Chi Lin, Wen-Jyi Hwang, and Chau-Jern Cheng
Department of Computer Science and Information Engineering, Department of Computer Science and Information Engineering, Department of Computer Science and Information Engineering, Department of Computer Science and Information Engineering, Institute of Electro-Optical Science and Technology, National Taiwan Normal University

Abstract— This paper present a novel FPGA-based hardware platform for realtime 3D reconstruction of digital holograms. The platform can be viewed as a hardware implementation of Fresnel transform for diffraction computation. The circuit employs a novel 2D FFT processor operating in fully pipelined fashion for accelerating the computation. Experimental results reveal that the proposed architecture has the advantages of high throughput, high accuracy and low power consumption for the 3D rendering and display.
Keywords— Holography; 3D Display; FPGA

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TW022  An Alternative Reading Eye for The Visual Impaired
Shih-Lun Chen, Hsin-Ju Tsai, Chiao-Yi Chien, and Ting-Lan Lin
Department of Electronic Engineer, Chung Yuan Christian University

Abstract— In this generation, everyone has the right to receive real-time and great amount of information. However, it is difficult for the visually impaired people to have the benefit of using this great information. In this paper, a reading system is proposed as an alternative eye for the visual impaired people. By this reading system, the information of words is transformed into the information of voice. It helps the visually impaired people to get all kinds of information quickly and easily. This system was developed based on the image processing technique, by which the captured image is converted into the text information by a character recognition technique. In order to achieve the demands of fast computing, multiple texts identification, huge database accessing, and real-time application, the very large scale integration (VLSI) technology was used to improve the performance of this system. This design was implemented by an Altera DE2-115a field programmable gate array (FPGA) board with a 5 Mega Pixel lens to capture the image of the book. For the future development, this system will be connected with the cloud systems, by which the recognized words can be translated into voice information by the cloud computing and tools. We hope this system can help the visually impaired people to get information from the books and papers independently.
Keywords— FPGA; image segmentation; image zooming; text detection; visual impaired people; VLSI; word identification

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