Altera InnovateAsia FPGA Design Contest –
5G Algorithm Innovation Competition
|Contest Materials Submission||
|Scope of the Contest Materials||
Note: The awards are listed as amounts before tax; the winners are obligated to comply with the applicable income tax law in China and pay tax for the awards they receive from the Competition. Awards payout to winners will be the amount listed in the program less any deductible tax according to Chinese law.
- From May 11, 2015 to June 11, 2015, please fill in the required information thru the online registration form.
- Successful registrar will receive a system generated confirmation letter and an ID number.
- Participants can use the ID number to login to the competition web site, to modify personal information and to submit contest materials.
Algorithm Design Paper
- Please read the algorithm descriptions in this website, and in your paper, please provide detail descriptions of your design methodology and steps; and highlight any unique features of your design.
- Contestants must use Altera hardware platform ( DE5-Net Dev Kit ) for the design.
About the 1st round competition
- Each participant is required to sign a Participant Release Form | Sample
- Before August 23, 2015, Contestants use their account password to login to the competition website, fill in personal information and submit contest materials for their choice of competing algorithm(s).
- Design paper: please reference outstanding works from past competitions
About 2nd (final) round competition
- Teams that are enlisted into the final round competition must use Altera’s design kits to complete the hardware implementation of the selected algorithm submitted in 1st round competition.
- Below actions must be completed before December 6, 2015：
- Use your account password to login the contest website, and submit the final complete design and documents.
- Please mail the physical design package to the competition organizer for final evaluation. Organizer will provide the delivery/mailing address (note: postages and delivery charges shall be borne by the contestants).
- Please indicate on the delivery package [5G Algorithm Innovation Competition].
Note: Acceptance of contestant’s materials is based on the date of receiving the physical design package by the organizer; the organizer will not be responsible for any postal delay; The receipt of the registered mail will not be taken as proof of receiving the physical design package by the organizer.
- If participant has any questions, please contact the organizer Miss Yin before December 6 (tel: 027-8774-5390 ext 8061).
About the final round competition
- The panel judges will select winning teams from all project submissions.
- Senior technical experts from Altera and Terasic
- Senior technical experts in the industry
- Domestically well-known scholars
- Evaluation Principle
- Technical capability (the best combination of the algorithmic advancement and FPGA implementation efficiency)
- Innovations (creativeness of the design methodology or implementation)
- Effectiveness (readiness to be applied to real-world applications and volume production)
- A comprehensive document is a plus and will be considered as part of the evaluation.
- Evaluation will be done according to the grading standard as provided below; decisions by the evaluation committee will be final and shall not be revoked.
- Grading Standard: The ranking of works by the contestants are determined based on the followings factors:
- Ø 1st phase: Algorithmic design & simulation
- Level of understanding to the algorithm as demonstrated in the submitted paper and simulation results
- Functional accuracy and performance of the simulated results
- Feasibility of FPGA implementation (high level proposal, any estimation of resource and performance)
- Ø 2nd phase: Algorithmic development & optimization
- Novelty and originality of the derived solution to address the targeted algorithm.
- Documentation completeness (including, but no limited to detail description of the optimization process, test reports, user guides, summary of lesson learns, etc)
- Functional accuracy and performance of the hardward implementation results
- Effective use of FPGA resource (minimum resource, power, while meeting target performance, latency and functionalities)
- All else being equal, a more advance implementation will be considered a plus
- Email notification will be sent to the winners with public announcement on the website.
- The winners’ designs will be published on this website by Terasic after the contest.
- Time and location of the prize presentation will be announced later.